A variety of operations are performed in memory devices, such as dynamic random access memory devices (“DRAM”), each of which affects the rate at which the memory device consumes power. One operation that tends to consume power at a substantial rate is the refresh of memory cells in the DRAM device. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. This refresh is generally performed on a row-by-row basis at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes. Since refresh essentially involves reading data bits from and writing data bits to a large number of memory cells, refresh tends to be a particularly power-hungry operation. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
The amount of power consumed by refresh also depends on which of the several refresh modes is activated. A self refresh mode is normally activated to automatically refresh memory cells or selected memory cells during periods when data are not being read from or written to the DRAM device. Since portable electronic devices are often inactive for substantial periods of time, the amount of power consumed during self refresh can be an important factor in determining how long the electronic device can be used between battery charges.
Another approach to reducing the rate at which power is consumed by a refresh operation is to refresh less than all of the memory cells in the DRAM device by refreshing only those memory cells needed to store data for a given application. In one technique, a software program is executed in a computer system containing the DRAM devices, and is analyzed to determine the data storage requirements for the program. The DRAM device then refreshes only those rows of memory cells that are needed to store the program data. In another technique, the DRAM device may operate in a partial array self refresh (“PASR”) mode. In the PASR mode, a mode register is programmed by a user to specify a region of memory cells that will be used and thus must be refreshed. The remaining memory cells are not used and thus need not be refreshed during at least some of the refresh modes. For example, the DRAM device may be partitioned into two regions, where one region contains critical data that is important to refresh and maintain, such as processor instructions, while the other region contains less critical data that can be lost if it is not refreshed, such as image data. Since processor instruction data is typically much smaller compared to image data, power consumption can be significantly reduced by refreshing only the region with the critical data.
Although the techniques for refreshing less than all of the memory cells can substantially reduce the rate of power consumption, it can nevertheless require a substantial amount of power to refresh the cells that are to be refreshed. Additionally, although a user is able to select a partial array self-refresh mode instead of the full self-refresh mode to reduce the power consumption rate, the memory cells selected for the partial array self-refresh are hardwired in the device at the time of manufacture and cannot be changed by the user. Therefore, if the selected partial self-refresh region contains inherent defects, another region of memory that can be more efficiently refreshed cannot be reselected. When a certain number of memory cells become defective such as, for example, as a result of a shorted memory cell capacitor, delays to the memory access may result due to the defective memory cell. The memory access must consequently be redirected to a different memory cell so that data will be accurately read from a DRAM. Redundant rows of memory cells are typically provided for this purpose. However, substantial additional circuitry must be provided to redirect memory accesses to redundant memory cells, which adds further delays to refresh operations.
There is therefore a need for an improved memory device, system and method, such as those that can be organized in a manner that allows, e.g., a user to custom select an optimal region of the memory device having the least number of defects to enable the best refresh rate.